A BDD based tool for the formal verification of concurrent systems using a propositional branching-time temporal logic: action computation tree logic (ACTL). It runs under different OS, including Linux and Windows 95/98/NT.

A temporal logic designed to specify properties of hardware at the register transfer level.

A flexible notation for both propositional and first-order reasoning about periods of time found in descriptions of hardware and software systems. Includes table of contents, abstracts and pdf downloads.

JMCA is an Java application for formally verifying finite-state concurrent systems using temporal logic formulas (ltl formulas).

A collection of papers by Shinji Kono on the Interval Temporal Logic.

First in a series of posts to the www-math mailing list on using TL operators in web pages. Clicking [Prev] will continue through the series.

A general tool for verifying the correctness of distributed software (designs) in a rigorous and mostly automated fashion. Can be used as a full linear temporal logic model checking system.

The Stanford Encyclopedia of Philosophy entry on the subject, with a detailed description, application areas and a bibliography.

A case study applying temporal logic to specify the operation of a bank of identical elevators servicing a number of floors in a building.

A survey of the field by Jan Chomicki and David Toman. From the 1997 BRICS Lecture Series.

Provides automatic verification of protocols and reactive systems through temporal logic specifications.

A logic for specifying and reasoning about concurrent systems.

The annual International Workshop on Temporal Representation and Reasoning covers temporal representation and reasoning, including temporal logic.